Delay locked loops are well known in the art for monitoring and adjusting delays of timing signals used with circuitry on integrated circuits, where the delays through the circuitry can vary with the changing conditions experienced by the integrated circuits. For example, higher temperatures can increase the delay through circuit components. Similarly, fluctuations in the voltage supply provided to an integrated circuit can cause the delays through the circuit components to fluctuate, where higher voltages may reduce delays and lower voltages may increase delays. Such delay variations can also be affected by processing variations during the manufacture of the integrated circuits.
In order to provide precise timing for signals and account for the variation in delay through the circuit components, delay locked loops typically include replicas or dummy-versions of the circuit components in a feedback path through which a periodic signal such as a clock signal is propagated. Delay lines included in the delay locked loop delay the periodic signal for a variable amount of time in order to achieve a desired phase relationship between a signal used to time operations performed on the integrated circuit and the periodic signal. As frequencies of clock signals used on and with integrated circuits increase, thereby resulting in shorter periods for those clock signals, the total delay through a delay locked loop can be longer than the time for a single period of the clock signal provided to the delay locked loop. In other words, a first positive edge of the clock provided to the loop may not have exited the delay locked loop before the next positive edge has entered the loop. In such systems, the number of clock cycles of delay through the delay locked loop can be important in terms of determining in which clock cycle certain events occur. Thus, while the delay locked loop may provide desirable phase alignment for a timing event with respect to a clock signal, it may also be necessary to ensure the event occurs in the correct clock cycle.
Therefore, it is desirable to provide techniques for determining a number of clock cycles of delay through a delay locked loop with minimal interference with the operation of the delay locked loop.